The subject invention may be viewed essentially as an improvement on storage control systems of the type disclosed in U.S. Pat. No. 3,699,530, granted Oct. 17, 1972 to R. S. Capowski et al and assigned to the assignee of the present application.
A principal object of the present invention is to increase the capacity and rate of information handling in such systems in an economical and efficient manner.
This is accomplished presently by: (1) adapting such systems to be able to operate relative to groups of channels as if they are effectively single channels: (2) arranging input busing to accommodate channel request input flow word-serially relative to a three-word-wide storage interface; (3) handling storage input of four data words from one channel in response to a single request (to speed up input flow); (4) providing quasi-asynchronous transfer of request unit inputs from any channel group when space exists in any associated request buffer; and (5) providing logical intra-group tagging suitable for resolving out-of-sequence interleaved accesses to storage from a group without delaying transitions of associated input buffers from busy to vacant status (i.e., without potentially slowing down input flow).
In connection with the above-mentioned logical tagging a two-bit counter ("In Tag Generator") associated with each channel group is advanced progressively (Modulo 4) in the order of reception of requests by the CBC from the respective group. The state of each tag counter is stored as tag information (Group In Tag), in association with the channel request, in the input buffer (In Buffer array). Buffer ID tag information designating the selected space in the In Buffer array is also stored in association with the request. As information is passed from the In Buffer array to Processor storage the associated Group In Tag and Buffer ID tag are passed to a FIFO queue (source/sink chain) which circulates its contents in time coordination with the outflow of associated information from processor storage (store acknowledgments and fetch data). The output from processor storage is placed in a partitioned Out Buffer array. The space selected is that designated by the Buffer ID information held in the source/sink (i.e., the space corresponding to the In Buffer space occupied by the associated request). As information is removed from the Out Buffer a two-bit counter (Out Tag Generator) associated with the respective group is advanced progressively (Modulo 4). The state of the Out Tag count for each group is compared to In Tags presented at the source/sink output in positional association with Buffer ID tags issued by the source/sink. An occupied space in the Out Buffer array is eligible for transfer out to the respective channel group only if its associated In Tag matches the current Out Tag of its group. Consequently even if storage accesses of a group are taken out of the sequence of input of respective requests to the CBC the outputs for that group will invariably be taken in that input sequence.
The foregoing practice in respect to Buffer ID tag and Group In tag usage permits In Buffer array sections to be marked as vacant as soon as access to storage is available for the respective section, without regard to the intra-group sequence of access to storage. In earlier systems a logical dependency between input buffer occupancy and resolution of output buffer flow presents a potential delay to (obstruction of) input flow.
Another feature of the invention is that channel identity information passed to the subject Channel Bus Controller with each group request circulates through the In Buffer array, the source/sink chain and the Out Buffer array; returning to the respective channel group with the output associated with the original request. Consequently requests of any group can be treated by the subject Bus Controller in a mode transparent to specific channel origins (i.e., as if from a single channel), thereby simplifying handling in the CBC.